Vertical nanowire MOSFETs allow for small foot-prints of thin channels with good electrostatic control provided by the gate-all-around geometry. Reducing the nanowire diameter improves electrostatics and reduces the foot-print area, but has shown to increase the extrinsic series resistance. High-precision doping control along the axial direction of the nanowire has proven insufficient and very challenging. Thinner nanowire diameters also increase the metal-semiconductor contact resistance since a smaller area is contacted. Furthermore, ohmic contacts typically require a high temperature annealing process to achieve sufficient low specific contact resistivity, whereas the electrical and structural properties of the gate dielectric are sensitive to high temperature processes. Gate-last processes are often used in planar technologies, where the source- and drain regions and their electrical contacts are fabricated prior to the gate definition.